Thick wafers cause an increase in capacitance, requiring thicker transmission lines, and, in turn, a larger IC footprint. In contrast, thinned wafers have the benefits of reduction in transmission line thickness, IC miniaturization, improved heat dissipation, and realization of stacked configuration in packaging. Stacked configuration is particularly useful for compact electronic products such as cellular telephones. By stacking and interconnecting devices vertically, device interconnection density and corresponding reductions in signal delay (as a result of shortening the distance between electrical connection points) can be significantly increased.
Silicon wafers used in high-volume integrated circuit production are typically 200 or 300 mm in diameter and have a through-wafer thickness of about 750 microns. Without thinning, it would be nearly impossible to form backside electrical contacts that connect with front-side circuitry by passing the connections through the wafer. Highly efficient thinning processes for semiconductor-grade silicon and compound semiconductors based on mechanical grinding (back-grinding) and polishing as well as chemical etching are now in commercial use. These processes allow device wafer thickness to be reduced to less than 100 microns in a few minutes while maintaining precise control over cross-wafer thickness uniformity.
Device wafers that have been thinned to less than 100 microns, and especially those thinned to less than 60 microns, are extremely fragile and must be supported over their full dimensions to prevent cracking and breakage. Various wafer wands and chucks have been developed for transferring ultra-thin device wafers, but the problem still exists on how to support the wafers during back-grinding and TSV-formation processes, because these steps impose high thermal and mechanical stresses on the device wafer as it is being thinned or after thinning. An increasingly popular approach to ultra-thin wafer handling involves mounting the full-thickness device wafer face down to a rigid carrier with a polymeric adhesive, to form a bonded stack. It is then thinned and processed from the backside. The fully processed, ultra-thin wafer is then removed, or debonded, from the carrier after the backside processing has been completed.
In debonding the bonded stack, particularly in an automatic process, complicated mechanical mechanisms such as robot arms must be employed to manipulate the stack using strong but non-uniform mechanical force, to execute motions like sliding, lifting, and twisting. As thinned wafers are extremely fragile, defects associated with this approach include device wafer breakage and damage within the microscopic circuitry of individual devices, which lead to device failure and yield loss. Moreover, complicated mechanical mechanisms also suffer from the disadvantages of higher cost, difficult operation, and lower efficiency.
Therefore, there exists a need for new approaches for debonding a carrier-workpiece bonded stack that can enhance the efficiency, simplify the procedure, provide high wafer throughput, and reduce or eliminate the risks for device wafer breakage and internal device damage. Advantageously, the present invention provides a solution that can meet such a need.